Qualified applicants will possess the following skills / experience:
Hands on expertise on handling DFT on hierarchical designs.
Hands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.
Hands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.
Hands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.
Hands on expertise SCAN pattern simulations and debug.
ATPG with the pattern delivery to the test engineering team.
Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.
Should have good post silicon DFT bring-up and debug experience.
Should have a good knowledge in simulation debug and prior experience at SoC level.
Excellent written and verbal communication skills.
Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
Bachelors/Masters in Electronics or equivalent degree with 10+ years of experience
|Primary skills||DFT on hierarchical designs.|
|Education||Bachelors/Masters in Electronics or equivalent degree|