- Define and develop verification architecture
- Define and develop verification methodologies
- Define and develop verification environments
- Write verification specifications, verification plans, and documentation
- Generate test bench and automatic regression plans
- Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs
- Complete block-level verification and chip level verification
- Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
- Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities
- Mentor Junior Engineers on need basis
- At least 8 years of industry work experience.
- Languages (Must) : Verilog and System Verilog.
- Methodologies (Any one) : OVM, VMM., UVM.
- EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog.
- Good understanding of digital design fundamentals.
- Proficient with Unix environment and common scripting languages.
- Expertise in test plan development.
- Expertise in Functional / Code Coverage activity.
- Experience in IP level verification activities.
- Hands on project experience in coverage/assertion driven verification
- Testbench development in Verilog/SystemVerilog using verification methodology
- Strong in simulation and debugging skills..
- Good knowledge of AMBA protocols like APB,AHB and AXI.
- Knowledge of revision control tools like CVS and GIT.
- Should be able to handle tasks independently.
- Good communication skills and the ability to work in a team environment.
- Experience with processor-based verification.
- Experience in UVM methodology.
|Skills||Verilog and System Verilog.|
|Primary skills||Verilog and System Verilog.|