To support Physical Design-related project activities for the MPU32, MCU32, WSG and CPG Business Units in Microchip. The product’s focus is on 32-bit microprocessors, microcontrollers, and wireless design and implementation.
- Timing closure support to maximize process node capability.
- Clock tree setup/debug and synthesis for optimal QoR.
- General physical implementation procedures.
- Multi-voltage island-based floorplan design and support.
- Flow development and automation implementation.
- Delivering Physical Verification-clean designs.
- Die size estimation and Bond out approval.
- Interfacing with external vendors and IP sources to resolve problems.
- Working with members from international design/implementation teams.
The successful candidate will have a minimum of 12+ years or more applicable technical experience in the physical and timing-related aspects of IC design. The design task requires experience in the following Physical Design-related activities:
- Advanced knowledge of VLSI logic principles, clock tree synthesis & debug, and design timing closure.
- Advanced knowledge of place and route methodologies and low power methodologies.
- Experience with 40nm or 28nm technologies is required.
- Detailed systems-level floorplanning.
- Power network planning.
- Multi-voltage/low power implementation techniques.
- Power integrity and reliability (EM & IR) analysis.
- The successful candidate should have:
- Detailed knowledge of ICC/ICC2 or Innovus and Redhawk toolsets.
- Proficiency in Tcl and Perl scripting is essential.
- Excellent debugging and analytical skills.
- Good verbal and written communication skills and strong interpersonal skills.
|Primary skills||MPU32, MCU32, WSG|
|Education||B.Tech or Equivalent Degree|