Development of CMOS/Finfet standard cell libraries for high speed, low power, automotive products using different foundry/process technologies. Expertise in Standard Cells Library characterization (Liberate/Siliconsmart). Perform Characterization Including NLDM, CCS and validate Standard Cell Libraries. Exposure to AOCV, LVF model characterization is plus. Write and simulate behavioral Verilog models for standard cells. Create EDA views and perform validation of library views. Scripting using Python, Perl is Plus. Release Standard Cell Libraries with Quality Checks.

Responsibilities:

• Standard Cells Library characterization (Liberate/Siliconsmart)
• Standard Cells Library integration (verilog/fastscan views, lib package generation)
• Electrical simulations (COSIM/spice simulators)
• Scripting using Python/Tcl/Perl
• APL Characterization using RedHawk.

Requirements/Qualifications:

• Preferred Skills
• Advanced Experience with Library Characterization Tools (Liberate preferred)
• Strong understanding of CMOS and FinFet technologies.
• Experience with electrical simulators (Hspice/Spectre/eldo)
• Strong debugging and problem-solving skills in the areas of cell design, spice simulation and characterization.
• Experience with Verilog models and Liberty files
• Scripting skills (Python/Tcl/Perl)
• Good written and oral communication skill.